1. Field of the Invention
This invention relates to semiconductor wafers, and more particularly, to a semiconductor stacked package and a method of fabricating a semiconductor stacked package.
2. Description of Related Art
When the area of a plat semiconductor package is fully occupied by a variety of electronic elements, a wafer stacked technology is brought to the market. A plurality of similar or different chips may be stacked on one another, to achieve multi-functionality.
FIGS. 1A and 1B illustrate a method of fabricating a semiconductor stacked package 1 according to the prior art. A block layer 100 is formed on a glass board 10. A wafer 11 comprised of a plurality of chips 11′ is stacked on the block layer 100. A cutting line L is formed among the chips 11′. Therefore, the wafer 11 can be cut into the plurality of chips 11′.
The wafer 11 includes a trace structure 110, and the trace structure 110 includes at least a dielectric layer 110a, a trace (not shown) formed on the dielectric layer 110a, and conductive pads 110b and 110c. 
A one-time cutting process is performed along the cutting line L so as to form a plurality of semiconductor stacked packages 1.
Since the singulation process in the prior art is performed in one time, a stress applied to the chips 11′ will extend and concentrate to a center of the chips 11′. As a result, a central region (indicated by a label K shown in FIG. 1C) of the chips 11′ is easily cracked or damaged, and the chips 11′ would even be useless.
Therefore, it is an important issue to overcome the problem of the prior art that a stress extends to the inside of the chips.